Near Field Communication (NFC) enables contactless short range communication between two devices, typically requiring a short-range distance of 4 cm or less to initiate a connection. NFC connection is much faster than other communication technologies such as Bluetooth or Wi-Fi. A user is only required to bring two NFC-supported devices within reading range to transfer data therebetween automatically. NFC applications include, but are not limited to, credit card payment, ticketing, content sharing, quick pairing.
NFC-supported devices may operate either as a NFC reader or a NFC card or tag which modulates information bits with a carrier frequency of 13.56 MHz. In a typical NFC receiver, a received NFC modulated signal is sampled either after downconversion or after envelope detection. This is because older CMOS technology, such as 0.35 u or 0.18 um, only affords low resolution and low sampling frequency of analog to digital conversion.
FIG. 1A shows an existing NFC receiver architecture with zero intermediate frequency. The analog front end consists of a direct in-phase and quadrature-phase analog mixer to downconvert a received signal to baseband signal, an analog filter to filter out higher frequency components of the mixer output, a VGA to amplify the filter output, and an analogue digital convertor (ADC) to convert the VGA output into a digital signal. A low resolution ADC is normally adopted for NFC amplitude shift keying (ASK) or binary phase-shift keying (BPSK) demodulation.
However, the architecture of FIG. 1A is expected to have the following drawbacks: high complexity at analog front end before sampling the RF signal; requires in-phase and quadrature-phase clock generation; overall area of analog and digital silicon area is large; does not utilize strong baseband processing in current mobile devices or Tablet PCs.
FIG. 1B shows an existing envelope detector based NFC receiver architecture. The analog front end consists of a diode based envelope detector, a high pass filter to remove direct current (DC) offset, a gain amplifier to amplify the signal, a low pass filter to filter RF carrier and its harmonics, and a comparator to digitize data for further processing. Compared to the architecture of FIG. 1A, the architecture of FIG. 1B does not require local oscillator mixing or high resolution ADC in the receiver chain.
However, the architecture of FIG. 1B is expected to have the following drawbacks: receiver sensitivity is limited, signal with low modulation index may pose problems; higher noise compared to other architecture; only amplitude demodulation is possible and may have NFC communication hole issue.
In view of the above and other issues, higher resolution and higher sampling frequency are desirable.